Our systems are now restored following recent technical disruption, and we’re working hard to catch up on publishing. We apologise for the inconvenience caused. Find out more

Recommended product

Popular links

Popular links


Designing Digital Computer Systems with Verilog

Designing Digital Computer Systems with Verilog

Designing Digital Computer Systems with Verilog

David J. Lilja, University of Minnesota
Sachin S. Sapatnekar, University of Minnesota
No date available
Paperback
9780521045728
Paperback

    This book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioural and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers.

    • This approach combines tools and methods of VLSI design
    • Uses industry-standard Verilog hardware description software
    • Complete ground-up approach covers all aspects of a real microprocessor design

    Product details

    No date available
    Paperback
    9780521045728
    176 pages
    243 × 168 × 9 mm
    0.297kg
    5 tables

    Table of Contents

    • Preface
    • 1. Controlling complexity
    • 2. A verilogical place to start
    • 3. Defining the instruction set architecture
    • 4. Algorithmic behavioral modeling
    • 5. Building an assembler for VeSPA
    • 6. Pipelining
    • 7. Implementation of the pipelined processor
    • 8. Verification
    • Appendix A: the VeSPA instruction set architecture (ISA)
    • Appendix B: the VASM assembler
    • Index.
    Resources for
    Type
    Web Link