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Testing of Digital Systems

Testing of Digital Systems

Testing of Digital Systems

N. K. Jha, Princeton University, New Jersey
S. Gupta, University of Southern California
May 2003
Available
Hardback
9780521773560
£110.00
GBP
Hardback
USD
eBook

    Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis. The book includes detailed treatment of the latest techniques including test generation for various fault models, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.

    • Most comprehensive book yet on digital systems testing
    • Covers all the latest techniques
    • Includes System-on-a-Chip testing

    Product details

    May 2003
    Hardback
    9780521773560
    1016 pages
    256 × 180 × 49 mm
    2.185kg
    90 tables
    Available

    Table of Contents

    • 1. Introduction
    • 2. Fault models
    • 3. Combinational logic and fault simulation
    • 4. Test generation for combinational circuits
    • 5. Sequential ATPG
    • 6. IDDQ testing
    • 7. Functional testing
    • 8. Delay fault testing
    • 9. CMOS testing
    • 10. Fault diagnosis
    • 11. Design for testability
    • 12. Built-in self-test
    • 13. Synthesis for testability
    • 14. Memory testing
    • 15. High-level test synthesis
    • 16. System-on-a-chip testing
    • Index.
    Resources for
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    Solutions (.pdf)
    Size: 616.93 KB
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    Chapter 14 - Memory Testing
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    Chapter 1 - Introduction
    Size: 565.5 KB
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      Authors
    • N. K. Jha , Princeton University, New Jersey

      Niraj Jha is Professor of Electrical Engineering at Princeton University and head of the Center of Embedded System-on-a-Chip Design, where his current research is focussed on the synthesis and testing of these devices. He is a fellow of IEEE, associate editor of IEEE Transactions on VLSI Systems and The Journal of Electronic Testing: Theory and Applications (JETTA) and a recipient of the AT&T Foundation award and the NEC preceptorship award for research excellence.

    • S. Gupta , University of Southern California

      Sandeep Gupta is an Associate Professor in the Department of Electrical Engineering at the University of Southern California, USA. He is Co-Director of the M.S. Program in VLSI Design, with research interests in the area of VLSI testing and design. He is a member of the IEEE.