Silicon Front-End Junction Formation — Physics and Technology

In this book researchers come together to highlight trends in research on the formation of ultrashallow junctions and their integration into devices. It is generally agreed that conventional RTP processes will not be able to reach the 45nm node of the ITRS. As alternatives, concepts based on solid-phase epitaxy or millisecond-flash annealing, and the use of impurities like fluorine or carbon, are discussed. An important issue for future devices is silicides and germanides. With a trend towards lower process temperatures, interest is directed towards nickel silicides. Of similar importance is the use of silicon-germanium layers in which dopant redistribution is affected by strain effects. Since process development and optimization are hardly conceivable without technology computer-aided design, the potentials and limitations of process simulation are addressed. Additional presentations focus on applications from atomistic modeling to the prediction of ultrashallow junction formation. Applications of state-of -the-art characterization methods are also demonstrated.